Detection of Stuck at Fault Indigital Circuits at Register Transfer Logic (RTL)

Due to the increasing complexity of modern circuit design, verification has become the major bottleneck of the entire design process. Most efforts are to verify the correctness of the initial Register-Transfer Level (RTL) descriptions written in Hardware Description Language (HDL).Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis.So in this paper, we detect the stuck-at fault using the concept of textio. Keywords-stuck-atfaults; fault coverage ;testpoints; validation sets